Handling   TLB Miss

When a TLB miss occurs, the system must determine how to find the correct virtual → physical address translation.

There are two possible approaches:

1. Hardware-managed TLB

2. Software-managed TLB (OS-managed)

Let’s break both down clearly.

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Hardware-Managed TLB

In this approach:

The hardware handles everything when a TLB miss occurs.

What Happens on a Miss?

1. Hardware detects TLB miss.

2. Hardware walks the page table in memory.

3. It finds the correct page-table entry (PTE).

4. It updates the TLB automatically.

5. It retries the instruction.

The operating system is not directly involved in handling the miss.

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What Hardware Needs

To do this, hardware must know:

• 📍 Where the page table is stored
  → via a page-table base register

• 📐 The exact format of the page table

• 🗂 How to walk multi-level page tables

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📌 Example Architecture

A classic example:

• Intel x86 architecture

  • Uses hardware page-table walking

  • The current page table base is stored in the CR3 register

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✅ Advantages

• Faster miss handling (no OS trap overhead)

• Transparent to OS during miss

❌ Disadvantages

• Hardware complexity

• Fixed page-table structure (less flexibility)

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Software-Managed TLB

In modern RISC architectures, the approach is different.

The OS handles the TLB miss.

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📌 Example Architectures

• MIPS R10000

• SPARC v9

These use software-managed TLBs.

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What Happens on a Miss?

Instead of walking the page table, the hardware:

1. Raises a TLB_MISS exception

2. Switches to kernel mode

3. Jumps to a trap handler in the OS

Then:

4. The OS looks up the page table.

5. The OS inserts the translation into the TLB using privileged instructions.

6. The OS returns from the trap.

7. The instruction is retried — now resulting in a TLB hit.

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⚠ Important Detail: Retrying the Instruction

This is subtle but crucial.

There are two types of traps:

Type	Resume At
System call	Next instruction
TLB miss	Same instruction

For a TLB miss:

The instruction must be re-executed.

Why?

Because the first attempt failed due to missing translation.After the TLB is updated, retrying will succeed.

Thus, hardware must save the correct PC depending on trap type.

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Avoiding Infinite TLB Miss Loops

Here’s a tricky problem:

What if the TLB miss handler itself causes TLB misses?

That would create an infinite loop.

Solutions include:

• 📌 Keep TLB handler in physical memory (no translation needed)

• 📌 Reserve permanent “wired” TLB entries for the handler

• 📌 Ensure handler code always hits in TLB

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⚖ Hardware vs Software TLB Management

Feature	Hardware-Managed	Software-Managed
Who walks page table?	Hardware	OS
Hardware complexity	High	Lower
OS flexibility	Low	High
Page table format	Fixed	Flexible

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Why Software Management Is Attractive

✅ Flexibility

The OS can use:

• Multi-level page tables

• Inverted page tables

• Hashed page tables

• Any custom structure

No hardware redesign needed.

✅ Simpler Hardware

On a miss, hardware just:

RaiseException(TLB_MISS)

The OS handles the rest.

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Big Picture

When a TLB miss happens, someone must:

1. Find the correct page-table entry

2. Update the TLB

3. Retry the instruction

Depending on the architecture:

• 🖥 Hardware does it (e.g., Intel x86)

• 🧩 OS does it (e.g., MIPS, SPARC)

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Key Insight

Hardware-managed TLB → Faster, but rigid
Software-managed TLB → More flexible, simpler hardware

Modern system design often prefers:

Simpler hardware + smarter OS