Memory Barriers

 

Memory Barriers (Memory Fences)

Why Memory Barriers Are Needed

Modern processors improve performance by reordering instructions and caching memory locally. While this is safe for single-threaded programs, it can cause incorrect behavior in concurrent programs where multiple threads or processes share data.

Because of this, one processor may not immediately see updates made by another processor, leading to race conditions and inconsistent results.

The rules that define how and when memory updates become visible to other processors are called the memory model.

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Memory Models

There are two main types of memory models:

1. Strongly Ordered Memory Model

• Any change made to memory by one processor is immediately visible to all other processors.

• Easier to reason about.

• Slower and rare in modern systems.

2. Weakly Ordered Memory Model

• Memory updates may not be immediately visible to other processors.

• Instructions may be reordered for performance.

• Used by most modern architectures (e.g., ARM, x86, PowerPC).

Because systems differ, kernel developers cannot assume a fixed memory behavior.

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What Is a Memory Barrier?

A memory barrier (or memory fence) is a special hardware instruction that enforces ordering of memory operations.

What It Guarantees

When a memory barrier is executed:

• All load and store operations before the barrier complete first

• No load or store after the barrier executes early

This ensures:

• Correct visibility of memory updates

• Correct ordering of instructions across processors

Even if the processor tries to reorder instructions, the memory barrier forces correctness.

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Example: Preventing Instruction Reordering

Without Memory Barrier (Problem)

Two threads share variables flag and x.

Expected behavior:

• Thread 2 sets x = 100, then sets flag = true

• Thread 1 waits for flag and then prints x

Due to reordering:

• flag might be updated before x

• Thread 1 may print x = 0 (incorrect)

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Using Memory Barriers (Solution)

In Thread 1:

while (!flag)
    ;
memory_barrier();
print x;

✔ Ensures flag is read before x

In Thread 2:

x = 100;
memory_barrier();
flag = true;

✔ Ensures x is written before flag

Now:

• Thread 1 always sees the correct value (x = 100)

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Memory Barriers and Peterson’s Solution

Peterson’s solution assumes:

• Instructions execute in program order

On modern CPUs:

• Instruction reordering can violate this assumption

• Both processes may enter the critical section simultaneously

Fix

By inserting a memory barrier between:

flag[i] = true;
turn = j;

we prevent reordering and restore correctness.

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Key Characteristics of Memory Barriers

• Very low-level

• Architecture-specific

• Mostly used by kernel developers

• Rarely used directly by application programmers

• Foundation for building higher-level synchronization primitives

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Summary Table

Aspect	Description
Memory Barrier	Hardware instruction enforcing memory order
Purpose	Prevent instruction reordering
Used In	Multiprocessor & multicore systems
Ensures	Visibility + ordering
Users	OS and kernel developers
Alternatives	Mutexes, semaphores (built on barriers)

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Final Takeaway

Memory barriers are essential in modern operating systems because:

• CPUs reorder instructions for speed

• Shared-memory concurrency requires strict ordering

• Software-only synchronization is not reliable

Memory barriers ensure that what you write is seen, and seen in the correct order.